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NJU3555
PRELIMINARY
4-BIT SINGLE CHIP OTP MICRO CONTROLLER
s GENERAL DESCRIPTION
The NJU3555 is the C-MOS 4-bit Single Chip OTP type Micro Controller with programmable Flash Memory. It is completely compatible with the NJU3505 in function and the pin configuration. Therefore, the NJU3555 is suitable for the final evaluation before NJU3505 mask generation, the small quantity production and short leadtime. * In this data sheet, only OTP programming and the difference between NJU3555 and NJU3505 are mentioned mainly. Therefore the detail function and specification should be referred on the NJU3505 data sheet. NJU3555FA1 NJU3555L
s PACKAGE OUTLINE
s FEATURES
q q q q q 8,192 X 8bits 8,128 X 8bits (Program area) 64 X 8bits (Option area) Internal Data RAM 256 X 4bits Wide operating voltage range 2.7V ~ 5.5V Package outline QFP44-A1 / SDIP42 (Compatible with NJU3505) ROM programmer "SUPERPRO/L" by XELTEK co,. Internal One Time Programmable ROM
s PIN CONFIGURATION IN OTP PROGRAMMING MODE
[ QFP44-A1 ] CNT2 Open CNT1 Open D7 D6 [ SDIP42 ]
CNT1 CNT2 VDD Open D5 D4 D3 D2 Open D1 D0 Open Open RESET PROM CLK REQ VSS VSS Open
1 2 Open 3 4 5 6 RESET PROM CLK REQ VSS 7 8 9 10 12 13 14 15 16 17 18 19 20 21 11
33 32 31 30 29 28 27 26 25 24 22 23
NJU3555FA1
Open
VDD
Open
VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Open D7 D6 VDD Open D5 D4 D3 D2 Open D1 D0
44
43
42
41
40
39
38
37
36
35
34
NJU3555L
Open
Note) The pin configuration in Normal operating mode is the same as NJU3505.
VSS
-1-
NJU3555
s BLOCK DIAGRAM
-2NJU3555
Interrupt
CPU CORE
Logic
VDD VSS
INT1
EXTI/PK0
INT2
TIMER1 STACK X Reg Y Reg AC
TEST RESET
INT3
CNTI/PK1
TIMER2 X' Reg MUX Y' Reg
TLU addr
PC
INT4
SDO/PL0
PRESCALER
SDI(O)/PL1
SIO OTP ROM ALU 8192 x 8 bits
OSC1
SCK/CKOUT
AIN0/PI0
CPU TIMING GENERATOR
OSC
OSC2
AIN1/PI1
AIN2/PI2
AIN3/PI3
IR RAM 256 x 4 bits ID
STANDBY CONTROLLER
AIN4/PA0
A/D
AIN5/PA1
AIN6/PA2
AIN7/PA3
VREF/PJ0
ADCK/PJ1
PORT_B
PORT_C
PORT_D
PORT_E
PORT_F
PORT_G
PORT_H
PF0
PF1
PF2
PB0
PB1
PB2
PB3
PE0
PE1
PE2
PE3
PC0
PC1
PD0
PD1
PD2
PD3
PH0
PH1
PG0
PG1
AVSS
AVDD
* Refer [INPUT OUTPUT TERMINAL TYPE]
NJU3555
s TERMINAL DESCRIPTION IN OTP PROGRAMMING MODE
No. NJU NJU 3555F 3555L 7 10 SYMBOL RESET D0 - D7 CNT1 CNT2 REQ CLK PROM VDD VSS INPUT / OUTPUT INPUT FUNCTION RESET terminal. When the low-level input-signal, the system is initialized.
25, 26, 28, 29, 28-31, 31-34, 34, 35 37, 38 1 40, 2 41 10 13 9 12 8 11 18, 33 21, 36 11, 12 14, 15 Note 1) 2)
INPUT/OUTPUT Data bus INPUT INPUT OUTPUT INPUT INPUT OTP control input terminal Request output terminal Clock input terminal OTP programming enable terminal Power Source (5V) Power Source (0V)
Use at VDD=5V in OTP programming mode. Non connect anything to the other terminals.
-3-
NJU3555
s Difference between NJU3555 (OTP version) and NJU3505 (MASK version)
q Operating mode NJU3555 has two operating modes. One is "Normal operating mode" and the other is "OTP programming mode".
*
Normal operating mode The "TEST" terminal is set to low level. (The terminal is recommended to connect to GND.) Operating voltage range; 2.7V ~ 5.5V. OTP Programming mode User program is read out from or written into the OTP by the universal programmer "SUPERPRO/L" and converting adapter made by XELTEK co,.(USA).
*
q
Programming memory (OTP)
The address location of programming memory (OTP) of NJU3555 is compatible with the masked ROM of NJU3505, excepting the option area. The option area is located in page 127(64bytes) in the following. Program Area Option Area : Addresses 0000H ~ 1FBFH : 8,128bytes : Addresses 1FC0H ~ 1FFFH : 64bytes
[ PROGRAM MEMORY AREA ] (Addresses)
0000H
Program Start Address (Addresses in the bank)
0000H 0040H
(Addresses in the page)
00H
Page 0 Page 1 Page 2
Bank 0
07FFH 0800H
0080H
64 Instruction Words
3FH
Bank 1
0FFFH 1000H 0780H
Bank 2
17FFH 1800H
07C0H 07FFH
Page 30 Page 31 Bank 0
8 Bits / Instruction Word 64 Instruction Words /Page 32 Pages / Bank 4 Banks / OTP * In case of NJU3505, Page127 is program area.
Bank 3
1FFFH 1FC0H 1FFFH
Option area Page 127
-4-
NJU3555
q Reset Terminal Type Internal Pull-up Resistance NJU3555 With Pull-up NJU3505 Without Pull-up
q
Option information set in the initialization
When the initialization is performed(RESET terminal is "L"), the operation information stored in option area is set as shown in the following timing chart . The option information is set in the term of 1 / fOSC x 512clock after RESET releasing and oscillation stability time. After information set, the program counter is set to 0000H and the NJU3555 operates in normal. [ TIMING CHART ] Oscillation Stability Time
Oscillator Clock
Option information setting 1/fOSCx512clock
Normal Operation
Oscillation Start
PC=0000H
RESET
fOSC=4MHz
about 128sec
-5-
NJU3555
s ABSOLUTE MAXIMUM RATINGS
(Ta=25C) PARAMETER Supply Voltage Input Voltage Output Voltage Analog Supply Voltage Analog Reference Voltage Analog Input Voltage Operating Temperature Storage Temperature SYMBOL VDD VIN VOUT AVDD VREF AIN0 ~ AIN7 Topr Tstg RATINGS -0.3 ~ +7.0 -0.3 ~ VDD + 0.3 -0.3 ~ VDD + 0.3 -0.3 ~ VDD + 0.3 -0.3 ~ AVDD + 0.3 -0.3 ~ AVDD + 0.3 -20 ~ +75 -55 ~ +125 UNIT V V V V V V C C
Note) The difference of electrical characteristics between NJU3555 (OTP version) and NJU3505 (MASK version) NJU3505
*Supply
NJU3555 2.7V
Voltage (VDD) MIN.
2.4V
*
Supply Current 5V (IDD1) Max. (IDD2) Max. (IDD3) Max. (IDD4) Max. (IDD5) Max. 3V (IDD1) Max. (IDD2) Max. (IDD3) Max. (IDD4) Max. (IDD5) Max.
1.2mA 1.2mA 1.6mA 4.0mA 4.0A 0.5mA 0.5mA 0.6mA 1.0mA 2.0A
30mA 30mA 30mA 30mA 20A 20mA 20mA 20mA 20mA 20A
-6-
NJU3555
s ELECTRICAL CHARACTERISTICS
SYM BOL VDD
DC CHARACTERISTICS 1-1
(VDD=3.6~5.5V, VSS=0V, Ta=-20~75C)
PARAMETER Supply Voltage
CONDITIONS
MIN 3.6
TYP
MAX 5.5 30
UNIT NOTE V mA *3
VDD VDD IDD1 VDD=5V, fOSC=2MHz X'tal Oscillation in Reset VDD IDD2 VDD=5V, fOSC=2MHz Ceramic Oscillation in Reset VDD IDD3 VDD=5V, fOSC=2MHz Supply Current CR Oscillation in Reset VDD IDD4 VDD=5V, fOSC=4MHz Operating (Except ADC) VDD IDD5 VDD=5V, STANDBY Mode AVDD IADD AVDD=VDD=5V, ADCK=225kHz AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1, PD0~PD3, PE0~PE3, VIH1 AIN0/PI0~AIN3/PI3, SDI(O)/PL1, SCK/CKOUT High-Level Input Voltage PF0~PF2, PG0, PG1, PH0, PH1, VIH2 VREF/PJ0, ADCK/PJ1, EXTI/PK0, CNTI/PK1, RESET OSC1 VIH3 AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1, PD0~PD3, PE0~PE3, VIL1 AIN0/PI0~AIN3/PI3, SDI(O)/PL1, SCK/CKOUT Low-level Input Voltage PF0~PF2, PG0, PG1, PH0, PH1, VIL2 VREF/PJ0, ADCK/PJ1, EXTI/PK0, CNTI/PK1, RESET OSC1 VIL3 *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister.
30
mA
*3
30
mA
*3
30 20 3.0 5.0
mA A mA
*3 *3 *3
0.7VDD
VDD
V
*1
0.8VDD VDD-1.0 0
VDD VDD 0.3VDD
V V V
*1
*1
0 0
0.2VDD 1.0
V V
*1
-7-
NJU3555
s ELECTRICAL CHARACTERISTICS
SYM BOL
DC CHARACTERISTICS 1-2
(VDD=3.6~5.5V, VSS=0V, Ta=-20~75C)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT NOTE
VDD=5.5V, VIN=5.5V AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1, PD0~PD3, PE0~PE3, High-Level IIH PF0~PF2, PG0, PG1, PH0, PH1, Input Current AIN0/PI0~AIN3/PI3, VREF/PJ0, ADCK/PJ1, EXTI/PK0, CNTI/PK1, SDI(O)/PL1, RESET, SCK/CKOUT VDD=5.5V, VIN=0V Without pull-up resistance AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1, PD0~PD3, PE0~PE3, IIL1 PF0~PF2, PG0, PG1, PH0, PH1, AIN0/PI0~AIN3/PI3, VREF/PJ0, ADCK/PJ1, EXTI/PK0, CNTI/PK1, Low-Level SDI(O)/PL1, SCK/CKOUT Input Current VDD=5.5V, VIN=0V With pull-up resistance AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1, PD0~PD3, PE0~PE3, IIL2 PF0~PF2, PG0, PG1, PH0, PH1, AIN0/PI0~AIN3/PI3, VREF/PJ0, ADCK/PJ1, EXTI/PK0, CNTI/PK1, SDI(O)/PL1, RESET, SCK/CKOUT IOH=-100A High-Level PD0~PD3, PE0~PE3, PF0~PF2, VOH Output Voltage PG0, PG1, PH0, PH1, SDO/PL0, SDI(O)/PL1, SCK/CKOUT IOL1=400A PD0~PD3, PE0~PE3, PF0~PF2, VOL1 PG0, PG1, PH0, PH1, SDO/PL0, Low-Level SDI(O)/PL1, SCK/CKOUT Output Voltage IOL2=15mA VOL2 AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1 VDD=5.5V, VOH=5.5V Output Leakage IOD AIN4/PA0~AIN7/PA3, PB0~PB3, Current PC0, PC1 Except VDD, VSS terminals Input Capacitance CIN fOSC=1MHz Other terminals : 0V *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister.
10
A
*1
-10
A
*1
-100
A
*1
VDD-0.5
V
*2
0.5
V
*2
2.0
V A pF
*2
10
*2
10
20
-8-
NJU3555
s ELECTRICAL CHARACTERISTICS
SYM BOL VDD
DC CHARACTERISTICS 2-1
(VDD=2.7~3.6V, VSS=0V, Ta=-20~75C)
PARAMETER Supply Voltage
CONDITIONS
MIN 2.7
TYP
MAX 3.6 20
UNIT NOTE V mA *3
VDD VDD IDD1 VDD=3V, fOSC=1MHz X'tal Oscillation in Reset VDD IDD2 VDD=3V, fOSC=1MHz Ceramic Oscillation in Reset VDD IDD3 VDD=3V, fOSC=1MHz Supply Current CR Oscillation in Reset VDD IDD4 VDD=3V, fOSC=2MHz Operating (Except ADC) VDD IDD5 VDD=3V, STANDBY Mode AVDD IADD AVDD=VDD=3V, ADCK=225kHz AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1, PD0~PD3, PE0~PE3, VIH1 AIN0/PI0~AIN3/PI3, SDI(O)/PL1, SCK/CKOUT High-Level Input Current PF0~PF2, PG0, PG1, PH0, PH1, VIH2 VREF/PJ0, ADCK/PJ1, EXTI/PK0, CNTI/PK1, RESET OSC1 VIH3 AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1, PD0~PD3, PE0~PE3, VIL1 AIN0/PI0~AIN3/PI3, SDI(O)/PL1, SCK/CKOUT Low-Level Input Voltage PF0~PF2, PG0, PG1, PH0, PH1, VIL2 VREF/PJ0, ADCK/PJ1, EXTI/PK0, CNTI/PK1, RESET OSC1 VIL3 *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister.
20
mA
*3
20
mA
*3
20 20 2.5 3.5
mA A mA
*3 *3 *3
0.8VDD
VDD
V
*1
0.85VDD VDD-0.3 0
VDD VDD 0.2VDD
V V V
*1
*1
0 0
0.15VDD 0.3
V V
*1
-9-
NJU3555
s ELECTRICAL CHARACTERISTICS
SYM BOL
DC CHARACTERISTICS 2-2
(VDD=2.7~3.6V, VSS=0V, Ta=-20~75C)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT NOTE
VDD=3.6V, VIN=3.6V AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1, PD0~PD3, PE0~PE3, High-Level IIH PF0~PF2, PG0, PG1, PH0, PH1, Input Current AIN0/PI0~AIN3/PI3, VREF/PJ0, ADCK/PJ1, EXTI/PK0, CNTI/PK1, SDI(O)/PL1, RESET, SCK/CKOUT VDD=3.6V, VIN=0V Without pull-up resistance AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1, PD0~PD3, PE0~PE3, IIL1 PF0~PF2, PG0, PG1, PH0, PH1, AIN0/PI0~AIN3/PI3, VREF/PJ0, ADCK/PJ1, EXTI/PK0, CNTI/PK1, Low-Level SDI(O)/PL1, SCK/CKOUT Input Current VDD=3.6V, VIN=0V With pull-up resistance AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1, PD0~PD3, PE0~PE3, IIL2 PF0~PF2, PG0, PG1, PH0, PH1, AIN0/PI0~AIN3/PI3, VREF/PJ0, ADCK/PJ1, EXTI/PK0, CNTI/PK1, SDI(O)/PL1, RESET, SCK/CKOUT IOH=-80A High-Level PD0~PD3, PE0~PE3, PF0~PF2, VOH Output Voltage PG0, PG1, PH0, PH1, SDO/PL0, SDI(O)/PL1, SCK/CKOUT IOL1=350A PD0~PD3, PE0~PE3, PF0~PF2, VOL1 PG0, PG1, PH0, PH1, SDO/PL0, Low-Level SDI(O)/PL1, SCK/CKOUT Output Voltage IOL2=5mA VOL2 AIN4/PA0~AIN7/PA3, PB0~PB3, PC0, PC1 VDD=3.6V, VOH=3.6V Output Leakage IOD AIN4/PA0~AIN7/PA3, PB0~PB3, Current PC0, PC1 Except VDD, VSS terminals fOSC=1MHz Input Capacitance CIN Other terminals : 0 *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister.
10
A
*1
-10
A
*1
-100
A
*1
VDD-0.5
V
*2
0.5
V
*2
1.0
V A
*2
10
*2
10
20
pF
- 10 -
NJU3555
s ELECTRICAL CHARACTERISTICS
SYM BOL
AC CHARACTERISTICS 1
(VSS=0V, Ta= -20~75C)
PARAMETER
CONDITIONS X'tal Resonator Ceramic Resonator External Resistor Oscillation External Clock X'tal Resonator Ceramic Resonator External Resistor Oscillation External Clock
MIN 0.03 0.03 0.03 0.03 0.03 0.03 0.03 0.03
TYP
MAX 2.0 2.0 1.0 2.0 4.0 4.0 2.0 4.0
UNIT
VDD=2.7~3.6V Operating Frequency fOSC VDD=3.6~5.5V
MHz
Instruction Cycle Time External Clock Pulse Width External Clock Rise Time Fall Time RESET Low-Level Width RESET Rise Time Port Input Level Width Edge Detection (PH1) Rise Time Fall Time Restart Signal (PH0) Rise Time External interrupt input (EXTI) Rise Time Fall Time CNTI Clock Frequency CNTI High-Level Width CNTI Rise Time Fall Time
tC tCPH tCPL tCPR tCPF tRST tRSR tPIN tEDR tEDF tSTR VDD=2.7~3.6V VDD=3.6~5.5V VDD=2.7~5.5V VDD=2.7~5.5V VDD=2.7~5.5V VDD=2.7~5.5V VDD=2.7~5.5V VDD=2.7~5.5V 6/fOSC 4/fOSC 250 125
6/fOSC 16600 16600 20
s ns ns s 20 ms s 200 200 ns ns
tEXR tEXF fCT tCT tCTR tCTF
VDD=2.7~5.5V
200
ns
VDD=2.7~5.5V VDD=2.7~5.5V VDD=2.7~5.5V 6/fOSC
fOSC/64
Hz s
200
ns
- 11 -
NJU3555
s AC CHARACTERISTICS 1
EXTERNAL CLOCK OSC1
TIMING CHART
1/fOSC VIH3 VIL3 tCPH tCPF tRST tCPL tRSR VIH2 VIL2 tCPR
RESET INPUT
RESET
PORT INPUT tPIN VIH1, VIH2 PORT VIL1, VIL2 EDGE DETECTOR INPUT tEDR VIH2 VIL2 RESTART SIGNAL INPUT tSTR VIH2 PH0 VIL2 EXTERNAL INTERRUPT tEXR VIH2 EXTI VIL2 TIMER2 EXTERNAL CLOCK TIMING CHART 1/fCT CNTI VIH2 VIL2 tCTR tCT tCTF tEXF tEDF
PH1
- 12 -
NJU3555
s ELECTRICAL CHARACTERISTICS
SYM BOL fSC
AC CHARACTERISTICS 2
SERIAL INTERFACE
(VSS=0V, VDD=2.7~5.5V, Ta= -20~75C) PARAMETER Serial Operating Frequency Clock Pulse Width Low-Level CONDITIONS Internal Clock External Clock
VDD=2.7~3.6V
MIN
TYP
MAX
UNIT
(1/12)xfOSC* Hz 500k fOSC=2MHz VDD=3.6~5.5V fOSC=4MHz VDD=2.7~3.6V fOSC=2MHz VDD=3.6~5.5V fOSC=4MHz 3.0 1.5 1.0 3.0 1.5 1.0 0.5 0.5 0.5 s s s s s
tSCL
Internal Clock External Clock
Clock Pulse Width High-Level
tSCH
Internal Clock
External Clock SDI setup Time tDS To SCK SDI Hold time tDH To SCK SDO Data t Fix Time To SCK DCD * The dividing ratio of the internal clock is 1/2.
s AC CHARACTERISTICS 2
SERIAL INTERFACE TIMING CHART
1/fSC tSCL tSCH VIH1
SCK VIL1
tDS SDI(O)
tDH VIH1
INPUT DATA VIL1 tDCD VOH
SDO/SDI(O) VOL1
OUTPUT DATA
- 13 -
NJU3555
s ELECTRICAL CHARACTERISTICS A/D CONVERTER CHARACTERISTICS
(VDD=AVDD=2.7~5.5V, VSS=AVSS=0V, Ta=25C, fOSC=4MHz) PARAMETER Resolution Absolute Accuracy Conversion Time Reference Voltage Analog Input Voltage ADCK Frequency SYMBOL tCONV VREF VIA fADCK VDD=5V, AVDD=5V, VREF=5V VDD=5V, AVDD=5V, VREF=5V 40 2.7 AVSS AVDD VREF 225 CONDITIONS MIN TYP 8 MAX 2 UNIT bits LSB s V V kHz
- 14 -
NJU3555
s OPTION as same as mask version (NJU3505)
1) INPUT OUTPUT Terminal Selection All of input-output terminals select a terminal type for each port from the following table1 and table2 by the mask option. [ CIRCUIT TYPE TABLE 1 ] TERMINAL TYPES Input / Output Terminal*1 SYMBOL Programmable Input / Output Port of Output Port of Input EXTRA FUNCTION REMARKS
AIN4 / PA0 AIN5 / PA1 AIN6 / PA2 AIN7 / PA3 PB0 PB1 PB2 PB3 PC0
IOP IO IOP IO IOP IO IOP IO IOP IO IOP IO IOP IO IOP IO
AD AD AD AD
Analog input to ADC (AIN4) Analog input to ADC (AIN5) Analog input to ADC (AIN6) Analog input to ADC (AIN7)
ICP ONP IC ON PC1 ICP ONP IC ON PD0 ICP OC IC PD1 ICP OC IC PD2 ICP OC IC PD3 ICP OC IC PE0 ICP OC IC PE1 ICP OC IC PE2 ICP OC IC PE3 ICP OC IC Note) The symbol in the above table is the same as in mask option generator software. *1) The symbol and the detail circuits of INPUT OUTPUT TERMINAL are written in INPUT OUTPUT TERMINAL TYPE.
- 15 -
NJU3555
[ CIRCUIT TYPE TABLE 2 ] TERMINAL TYPES Input / Output Terminal*1 SYMBOL Programmable Input / Output Port of Output Port of Input EXTRA FUNCTION REMARKS
PF0 PF1 PF2 PG0 PG1 PH0 PH1
ISP IS ISP IS ISP IS ISP IS ISP IS ISP IS ISP IS ICP IC ICP IC ICP IC ICP IC ISP IS ISP IS ISP IS ISP IS
OC OC OC OC OC OC OC Restart signal input Edge detection E D R F D With restart input Without restart input Rise edge detection Fall edge detection Without edge detection
AIN0 / PI0 AIN1 / PI1 AIN2 / PI2 AIN3 / PI3 VREF / PJ0 ADCK / PJ1 *2 EXTI / PK0 *2
AD AD AD AD AD
ACP AC IIP R Rise interrupt input II F Fall interrupt input IIP CNTI / PK1 II *2 SDO / PL0 OC SO MSB MSB first SDP LSB LSB first SDI(O) / PL1 ICP OC SD *2 IC SCP Serial clock input/output SCK / CKOUT SC *2 *3 Output clock divide by pre-scaler Note) The symbol in the above table is the same as in mask option generator software. *1) The symbol and the detail circuits of INPUT OUTPUT TERMINAL are written in INPUT OUTPUT TERMINAL TYPE. *2) The pull-up resistance is added to the terminal selected as the extra function. *3) When Serial INPUT-OUTPUT is selected, "SCK" is selected automatically. When it is not selected, "CKOUT" is selected automatically.
Analog input to ADC (AIN0) Analog input to ADC (AIN1) Analog input to ADC (AIN2) Analog input to ADC (AIN3) Reference input (VREF) External clock input (ADCK) External interrupt input (EXTI) External clock of Timer 2 input (CNTI) Serial data output Serial data input/output
- 16 -
NJU3555
[MASK OPTION LIST] SYM BOL ICP ISP IC IS ONP OC ON IIP II SDP SD SO SCP SC AD ACP AC IOP IO FUNCTION C-MOS input with pull-up resistance C-MOS Schmitt trigger input with pull-up resistance C-MOS input C-MOS Schmitt trigger input Nch-FET Open-Drain output with pull-up resistance C-MOS output Nch-FET Open-Drain output External interrupt resistance External interrupt input Serial data resistance input/output with pull-up input with pull-up SYM BOL R F D MSB LSB 1 2 3 4 5 6 7 8 9 a b c E D FUNCTION Rise edge detection Fall edge detection Prohibition of edge detection Serial data order MSB first Serial data order LSB first 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 1/512 1/1024 1/2048 1/4096 permission prohibit
Serial data input/output Serial data output Serial clock input/output with pull-up resistance Serial clock input/output A/D converter External clock input with pull-up resistance for ADC External clock input for ADC Programmable input/output with pull-up resistance Programmable input/output
- 17 -
NJU3555
[ INPUT OUTPUT TERMINAL TYPE ] Types With Pull-up Type ICP Without Pull-up Type IC Terminals PC0, PC1, PD0~PD3, PE0~PE3, AIN0/PI0~ AIN3/PI3, SDI(O)/PL1
C-MOS INPUT TERMINAL
Type ISP SCHMITT TRIGGER
Type IS
PF0~PF2, PG0, PG1, PH0, PH1, VREF/PJ0, ADCK/PJ1, EXTI/PK0, CNTI/PK1
Type ON
C-MOS OUTPUT TERMINAL
PD0~PD3, PE0~PE3, PF0~PF2, PG0, PG1, PH0, PH1, SDO/PL0, SDI(O)/PL1
Type ONP N-channel(Nch) OPEN DRAIN
Type ON
PC0, PC1
PROGRAMMABLE INPUT OUTPUT TERMINAL
Type IOP
Type IO
AIN4/PA0~ AIN7/PA3, PB0~PB3
C-MOS INPUT / Nch OPEN DRAIN OUTPUT
- 18 -
NJU3555
2) Re-start signal Input Selection PH0 terminal performs as the re-start terminal to return from "STANDBY" mode. It is selected by mask option. The STANDBY mode is released by the rising edge of the input signal to PH0 terminal, and the CPU restarts the execution from the last address before the STANDBY mode in.
3) Edge Detector Selection PH1 terminal is added the "Edge detect function" by the mask option. Rising edge Falling edge
4) External Interrupt of the edge Selection When the interrupt function is set by mask option. PK0 terminal performs as the interrupt input terminal. The polarity of the edge, rising as "low to high" or falling as "high to low", is selected by the mask option. Rising edge Falling edge
5) The data order (MSB, LSB) of the Serial Interface The data order of the Serial Interface is selected select either MSB or LSB first by the mask option.
6) A/D Control Clock A/D Control Clock is selected either the external clock from ADCK terminal or the internal clock from the prescaler by the mask option.
7) Dividing ration of the internal clock Each dividing ration of the count clocks of Timer1 and Timer2, the Internal shift clock of the Serial Interface, the clock of the A/D control clock and the output clock through the SCK/CKOUT terminal is selected among the following by the mask option. The frequency of each clock is determined by the dividing ration and the 1-instruction term (1/fOSCx6). 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024, 1/2048, 1/4096 Note) As Timer2 clock, the external clock or the internal is selected by the program. As the shift clock of the serial interface, the external clock or the internal is selected by the program.
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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